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DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
Table 1. Alarm Frequency Control
DY/DT
X
X
X
X
1
0
AM4
X
X
X
1
0
0
AM3
X
X
1
0
0
0
AM2
X
1
0
0
0
0
AM1
1
0
0
0
0
0
ALARM OCCURRENCE
Every second
Every minute, when the seconds match
Every hour, when minutes and seconds match
Every day, when hours, minutes, and seconds match
Every week, when day, hours, minutes, and seconds match
Every month, when date, hours, minutes, and seconds match
Multifunction Control/Setup Register
ADDR
134h
b7
0
b6
BME
b5
BTRP
b4
b3
WDOS
b2
WDE
b1
OSCE
b0
CAE
There is general read and write access to this address. Bit 7 always reads 0; it cannot be written to 1. This register
is reset to 00h when the battery voltage ramps up. See Figure 5 for the use of the CAE, WDE, WDOS, and BME
bits in the generation of the ALMZ, RSTZ, and WDOZ signals.
BIT DESCRIPTION
CAE: Clock Alarm
Enable
OSCE: RTC Oscillator
Enable
WDE: Watchdog Enable
WDOS: Watchdog
Output Selection
BTRP: Battery Monitor
Trip Point
BME: Battery Monitor
Enable
BIT(S)
b0
b1
b2
b3
b5:b4
b6
DEFINITION
Enable/disable control of the RTC /Calendar alarm.
Legend : 0 ? disabled (power-on default); 1 ? enabled
Run/halt control of the RTC ’s 32KHz oscillator
Legend : 0 ? halted (power-on default); 1 ? running
Enable/disable control of the watchdog and its alarm.
Legend : 0 ? disabled (power-on default); 1 ? enabled
The watchdog timer is reset by changing WDE from 0 to 1, V CC ramp up
(Power-on reset) or applying a positive pulse at the WDI pin.
Pin selection for watchdog alarm signaling.
Legend : 0 ? WDOZ pin (power-on default); 1 ? ALMZ pin
Selection of the nominal Battery Monitor Trip Point voltage.
Legend : 00b ? 1.75V (power-on default); 01b ? 2.00V;
10b ? 2.25V; 11b ? 2.50V
Enable/disable control of the Battery Monitor and its alarm.
Legend : 0 ? disabled (power-on default); 1 ? enabled
The battery test takes place a) after BME changes to 1, b) after V CC
ramps up, c) every hour on the hour. The RTC must be running (OSCE
= 1) for the battery monitor to function.
Alarm and Status Register
ADDR
135h
b7
0
b6
BATA
b5
WPZV
b4
POR
b3
BOR
b2
CLKA
b1
WDA
b0
RST
There is general read access to this address; writing clears all bits to 0. Bit 7 always reads 0. See Figure 5 for the
use of the CLKA, WDA, and BATA bits in the generation of the ALMZ, RSTZ, and WDOZ signals.
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